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A1174
Ultrasensitive Hall Effect Latch with Internally or Externally Controlled Sample and Sleep Periods for Track Ball and Scroll Wheel Applications
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Features and Benefits
Micro-power latch operation 1.65 to 3.5 V battery operation Push-pull output eliminates the need for an external pullup resistor User configured, internally or externally controlled sample and sleep periods Floating the two clock pins results in the use of a fixed sampling clock internal to the sensor Toggling the clock pins allows the user to control the sampling and sleep times of the sensor for extreme low power operation External control of the clock pins allows the user to implement synchronous sampling of multiple sensors in direction detection systems Chopper stabilization Superior temperature stability Extremely low switchpoint drift Insensitive to physical stress Solid state reliability Small size
Description
The A1174 is a micro-power, Hall-effect latch for use in portable devices that employ rotational detection systems, and have a power supply voltage between 1.65 and 3.5 V. The device has a single push-pull output structure and requires no external pull-up resistor for reliable operation. When a sufficient positive magnetic field is present on the device, the device output transitions to the low state and is latched in this state until a negative field of sufficient strength latches the device output into the high state. The latched output is ideal when using multiple sensors in rotational speed and direction sensing systems (for example, track ball and scroll bar systems in portable devices). The device includes an innovative clocking scheme that satisfies the micro-power needs of almost any application, including track balls for PDAs and cell phones. Using the EXTERNAL_CLK and DUAL_CLK pins as described in this datasheet, the device can be set into various working modes. In Dual Clock mode, the device switches between predefined slow and fast sampling rates. The average current consumption of the device is extremely low when rotation is not detected. In External Clock mode, the user sets the clock rate for the device to achieve the required on and off times for controlling average power. This user-determined clocking also helps to
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Package: 6-contact MLP/DFN (suffix EW)
1.5 mm x 2 mm x 0.40 mm
Not to scale
+B
Magnetic Flux Density
BOP 0 BRP -B +V
BOP BRP
BOP BRP
A1174 Output On Off On Off On
Figure 1. Timing diagram for output switching
A1174-DS
A1174
Ultrasensitive Hall Effect Latch with Internally or Externally Controlled Sample and Sleep Periods for Track Ball and Scroll Wheel Applications
Description (continued)
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achieve synchronous clocking of multiple devices. This allows a defined phase relationship between the output transitions of each device in direction detection systems. Improved stability is made possible through dynamic offset cancellation using chopper stabilization, which reduces the residual offset voltage normally caused by device overmolding, temperature dependencies, and thermal stress. Solid state reliability is provided
by integrating, on a single silicon chip, a Hall-voltage generator, a small-signal amplifier, chopper stabilization, a latch, and a MOSFET output. The device package is a 6-contact, 1.5 mm x 2 mm, 0.40 mm nominal overall height MLP/DFN, with exposed pad for enhanced thermal dissipation. It is lead (Pb) free, with 100% matte tin leadframe plating.
Selection Guide
Part Number Packing*
A1174EEWLT-T 3000 pieces per 7-inch reel *Contact Allegro(R) for additional packing options
Absolute Maximum Ratings
Characteristic Forward Supply Voltage Reverse Supply Voltage Output Voltage Reverse Output Voltage EXTERNAL_CLK and DUAL_CLK Pins Input Voltage EXTERNAL_CLK and DUAL_CLK Pins Reverse Input Voltage Continuous Output Current Magnetic Flux Density* Operating Ambient Temperature Maximum Junction Temperature Storage Temperature *1G = 0.1 mT (millitesla) Symbol VDD VRDD VOUT VROUT VIN VRIN IOUT(sink) IOUT(source) B TA TJ(MAX) Tstg Range E Notes Rating 5.0 -0.3 5.0 -0.3 5.0 -0.3 -1 1 Unlimited -40 to 85 165 -65 to 170 Units V V V V V V mA mA G C C C
Terminal List Pin-out Diagram
VDD 1 NC 2 VOUT 3 PAD 6 DUAL_CLK 5 GND 4 EXTERNAL_CLK
Number 1 2 3 4 5 6
Name VDD NC VOUT EXTERNAL_CLK GND DUAL_CLK Supply Voltage No connect Output
Function
In combination with DUAL_CLK , allows external control of the device sampling period and duty cycle Ground In combination with EXTERNAL_CLK , drives the part in Dual Clock mode
(Top View)
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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A1174
Ultrasensitive Hall Effect Latch with Internally or Externally Controlled Sample and Sleep Periods for Track Ball and Scroll Wheel Applications
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Functional Block Diagram
VDD
Amp
Latch
VOUT
Sample Control Block EXTERNAL_CLK DUAL_CLK Input Decoder Internal Clock GND
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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A1174
Ultrasensitive Hall Effect Latch with Internally or Externally Controlled Sample and Sleep Periods for Track Ball and Scroll Wheel Applications
Operating Characteristics Valid over full operating voltage and ambient temperature ranges (unless otherwise specified) www..com Characteristic Symbol Test Conditions Min. Typ.1 Max.
Electrical Characteristics Supply Voltage2 Output On Voltage VDD VOUT(SAT) IDD(EN) Supply Current IDD(DIS) IDD(AV) Internal Chopper Stabilization Clock Frequency EXTERNAL_CLK and DUAL_CLK Pins Input Current EXTERNAL_CLK and DUAL_CLK Pins Leakage Current Supply Slew Rate3 Normal Clock Mode Characteristics4 Normal Mode Awake Duration Normal Mode Period External Clock Mode Characteristics4 EXTERNAL_CLK and DUAL_CLK Pins Threshold External Clock Mode Awake Duration External Clock Mode Period State Transition Delay5 Dual Clock Mode Characteristics4 Dual Clock Mode Awake Duration Dual Clock Mode Fast Sampling Period Dual Clock Mode Slow Sampling Period Dual Clock Mode Timeout6 Magnetic Characteristics2 Operate Point Release Point Hysteresis
1Typical
Unit V V mV mV mA A A A kHz mA A V/ms ms ms V V ms ms ms ms ms ms ms
TA = 25C -40C TA 85C NMOS on, IOUT = 1 mA Chip in awake state (enabled) Chip in sleep state (disabled) Normal Clock mode, VDD = 2.5 V Normal Clock mode, VDD = 3.0 V VEXTERNAL_CLK = VDD, VDUAL_CLK = VDD VEXTERNAL_CLK = 0 V, VDUAL_CLK = 0 V tOFF = 100 ms
1.65 1.8 - - - - - - - - 0.1 - - - 0.25 x VDD
- - 100 - - - - 200 0.5 0.02 - 25 0.7 - - - - 25 25 8x tawake_dual 28 100 x tperiod_slow 36 -36 72
3.5 3.5 300 - 2.0 8.0 71 82 - - - - 38 1.05 0.75 x VDD - - - 38 38 - - -
VOUT(HIGH) PMOS on, IOUT = 1 mA
VDD - 300 VDD - 100
fC IIN IOFF SR tawake_norm tperiod_norm Vth(HIGH) Vth(LOW) tawake_ext tperiod_ext tdelay_ext tawake_dual tperiod_fast tperiod_slow ttimeout VEXTERNAL_CLK > Vth(HIGH) VEXTERNAL_CLK > Vth(HIGH)
38 80 - - - - -
BOP BRP BHYS
South pole to device branded side North pole to device branded side BOP - BRP
5 -55 -
55 -5 110
G G G
values are at TA = 25C and VDD = 2.75 V. Performance may vary for individual units, within the specified maximum and minimum limits. 2Magnetic operate and release points vary with supply voltage. 3If the device power supply is chopped, power-up slew rate dV DD / dt has to be adjusted to ensure correct functioning of the device. tOFF is the time of the power cycle when VDD < VDD(min). 4Defined in the Functional Description section of this datasheet. 5Time between external clock transition and resulting transition of the device between the awake and sleep states. See Functional Description section. 6If no output transition is detected during the timeout interval, the device goes back into slow sampling. See Functional Description section.
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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A1174
Ultrasensitive Hall Effect Latch with Internally or Externally Controlled Sample and Sleep Periods for Track Ball and Scroll Wheel Applications
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Characteristic Performance
Saturation Voltage versus Supply Voltage
300 250
Saturation Voltage versus Temperature
300 250 IOUT = 1 mA
VOUT(SAT) (mV)
VOUT(SAT) (mV)
200 150 100 50 0 -60 -40 -20 0 20 TA (C) 40 60 80 100
VDD (V) 1.65 1.8 2.5 2.75 3.0 3.5
IOUT = 1 mA
200 150 100 50 0 1.0 1.5 2.0 2.5 VDD (V) 3.0 3.5 4.0
TA (C)
85C -40C 25C
Average Supply Current versus Temperature
100 90 80 70 100 90 80 70
Average Supply Current versus Supply Voltage
60 50 40 30 20 10 0 -60 -40 -20 0 20 TA (C) 40 60 80 100
VDD (V) 1.65 1.8 2.5 3.0 3.5
TA (C)
85C -40C 25C
IDD(AV) (A)
IDD(AV) (A)
60 50 40 30 20 10 0 1.0 1.5 2.0 2.5 VDD (V) 3.0 3.5 4.0
Normal Mode Period versus Temperature
1000 900 800 700 1000 900 800
Normal Mode Period versus Supply Voltage
tperiod (s)
600 500 400 300 200 100 0 -60 -40 -20 0 20 TA (C) 40 60 80 100
VDD (V) 1.65 1.8 2.5 3.0 3.5
700
tperiod (s)
600 500 400 300 200 100 0 1.0 1.5 2.0 2.5 VDD (V) 3.0 3.5 4.0
TA (C)
85C -40C 25C
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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A1174
Ultrasensitive Hall Effect Latch with Internally or Externally Controlled Sample and Sleep Periods for Track Ball and Scroll Wheel Applications
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Dual Mode Fast Period versus Temperature
400 350 300
Dual Mode Fast Period versus Supply Voltage
400 350
tfast_period (s)
tfast_period (s)
250 200 150 100 50 0 -60 -40 -20 0 20 TA (C) 40 60 80 100
VDD (V) 1.65 1.8 2.5 3.0 3.5 3.5
300 250 200 150 100 50 0 1.0 1.5 2.0 2.5 VDD (V) 3.0 3.5 4.0
TA (C)
85C -40C 25C
Dual Mode Slow Period versus Temperature
50 45
t slow_period (ms) t slow_period (ms)
Dual Mode Slow Period versus Supply Voltage
50 45 40 35 30 25 20 15 10 5 0
40 35 30 25 20 15 10 5 0 -60 -40 -20 0 20 TA (C) 40 60 80 100
VDD (V) 1.65 1.8 2.5 3.0 3.5
TA (C)
85C -40C 25C
1.0
1.5
2.0
2.5 VDD (V)
3.0
3.5
4.0
Operate Point versus Temperature
75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 -60 -40 -20 0 20 TA (C) 40 60 80 100
Operate Point versus Supply Voltage
55 50 45
VDD (V) 1.65 1.8 2.5 2.75 3.0 3.5
BOP (G)
40 35 30 25 20 15 10 5 0 1.0
1.5
TA (C)
85C -40C 25C
B
OP
(G)
2.0
2.5
3.0
3.5
4.0
VCC (V)
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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A1174
Ultrasensitive Hall Effect Latch with Internally or Externally Controlled Sample and Sleep Periods for Track Ball and Scroll Wheel Applications
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Release Point versus Temperature
0 -5 -10 -15 -20
Release Point versus Supply Voltage
0 -5 -10 -15 -20
VDD (V) 1.65 1.8 2.5 2.75 3.0 3.5
BRP (G)
TA (C)
85C -40C 25C
BRP(G)
-25 -30 -35 -40 -45 -50 -55
-25 -30 -35 -40 -45 -50 -55
-60
-40
-20
0
20 TA (C)
40
60
80
100
1.0
1.5
2.0
2.5 VDD (V)
3.0
3.5
4.0
Hysteresis versus Temperature
110 100 90 80 70 60 50 40 30 20 10 0 -60 -40 -20 0 20 TA (C) 40 60 80 100 110 100 90
Hysteresis versus Supply Voltage
VDD (V) 1.65 1.8 2.5 2.75 3.0 3.5
B HYS (G)
80 70 60 50 40 30 20 10 0 1.0 1.5 2.0 2.5 VDD (V) 3.0 3.5 4.0
TA (C)
85C -40C 25C
BHYS(G)
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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A1174
Ultrasensitive Hall Effect Latch with Internally or Externally Controlled Sample and Sleep Periods for Track Ball and Scroll Wheel Applications
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Functional Description
This is illustrated in figure 3. The awake state duration, tawake_x , is common in all defined modes of operation. The sleep state duration is set at a longer duration than the awake period in order to conserve power. During the sleep state, current consumption is insignificant (equal to IDD(DIS)), but the device output does not switch in response to changing incident magnetic fields. The device shows maximum current consumption, IDD(EN) , during the awake state and minimal current consumption, IDD(DIS) , during the sleep state. Average current, IDD(AV) , for micro-power operation is derived from following formula: IDD(AV) = IDD(EN) x tawake_x + IDD(DIS) x tsleep_x tperiod_x Three micro-power control modes are available: * Normal Clock mode * External Clock mode * Dual Clock mode Selection of clock mode is determined by the configuration of the EXTERNAL_CLK pin and the DUAL_CLK pin, and applied voltages as illustrated in figure 4 and table 1. Normal Clock Mode When both device clock pins are left floating or are grounded, the internal timing circuitry activates the sensor for tawake_norm and deactivates it for the remainder, tsleep , of the duty cycle period, tperiod_norm. The short awake time .
Output State Operation The output state (VOUT pin) of this device switches to low (on) when an incident magnetic field, perpendicular to the Hall sensor, exceeds the operate point threshold, BOP . After turn-on, the output voltage is VOUT(SAT) (see figure 2). When the magnetic field is reduced below the release point, BRP , the device output goes high (off), VOUT(HIGH) . The difference in the magnetic operate and release points is the hysteresis, BHYS, of the device. This built-in hysteresis allows clean switching of the output even in the presence of external mechanical vibration and electrical noise. Removal of the magnetic field leaves the device output latched low (on) if the last crossed switchpoint is BOP , or latched high (off) if the last crossed switchpoint is BRP . Powering-on the device in the hysteresis range (less than BOP and higher than BRP) gives an indeterminate output state. The correct state is attained after the first excursion beyond BOP or BRP . Micro-power Operation Micro-power operation of the device involves duty cycle control achieved by: * powering all circuits in the chip and latching the device output state at the end of awake state periods, and * turning off the bias current to most circuits in the chip and maintaining the device output state through sleep state periods.
V+ Switch to High Switch to Low
VOUT(HIGH) (off)
IDD
tperiod_x
VOUT
IDD(EN)
tawake_x tsleep_x Sample and output latched
VOUT(SAT)(on) BRP B- 0 B+
IDD(DIS)
0 t
BOP
BHYS
Figure 3. Micro-power behavior of the device Figure 2. Device output switching logic
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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A1174
Ultrasensitive Hall Effect Latch with Internally or Externally Controlled Sample and Sleep Periods for Track Ball and Scroll Wheel Applications
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prior to sensor sampling and data latching on the falling edge of the timing pulse. The output during the sleep time, tsleep , is latched in the last sampled state.
External Clock Mode Applying a voltage greater than Vth(HIGH) to both clock pins puts the device into the awake state (without automatic cycling through the sleep state). The device uses the maximum defined supply current, reaching maximum power consumption. Applying a voltage greater than Vth(HIGH) to the EXTERNAL_ CLK pin and a voltage lower than Vth(LOW) to the DUAL_CLK pin puts the device into the sleep state (without automatic cycling through the awake state), and latches the device output in the output state determined during the prior awake state. The duration of the awake and sleep periods can be controlled externally by applying a voltage greater than Vth(HIGH) to the
EXTERNAL_CLK pin and applying an external clock to the DUAL_CLK pin. The user can define the input sampling time and frequency to reach a target consumption current level, but the minimum sample time must remain longer than tawake_ext. Note that the device should be periodically put into the awake state in order to update the device output state. State Transition Delay, text_delay , appears as the time between an external clock transition and the resulting transition of the device between the awake and the sleep state. This is illustrated in figure 5. Dual Clock Mode When the EXTERNAL_CLK pin is left floating, or is grounded, and the DUAL_CLK pin is pulled to a voltage greater than Vth(HIGH) , the device enters Dual Clock mode. Figure 6 gives an overview of the device operation algorithm in Dual Clock mode.
Table 1. Clock Mode Selection Options
Connection EXTERNAL_CLK Pin Low / NC High Low / NC DUAL_CLK Pin Low / NC High Low High Mode Normal Clock External Clock, Awake State External Clock, Sleep State Dual Clock Description Awake and sleep state durations defined by device internal clock Awake and sleep state durations defined by external clock Awake and sleep state durations defined by internal fast or slow clock
High = V Vth(HIGH) , Low = V Vth(LOW) , NC = no connect (float or connect to ground)
Power on
tsleep_ext
EXTERNAL_CLK pin high? YES NO Normal Clock Mode NO DUAL_CLK pin high? YES Dual Clock Mode DUAL_CLK pin high? YES External Clock Mode Awake State External Clock Mode Sleep State NO
tawake_ext
External Clocking
tdelay_ext
Internal Clocking Device Awake State Supply Current IDD(DIS)
tdelay_ext
Device Sleep State IDD(EN)
Figure 4. Clock mode selection algorithm; determined by clock pins connections in the application
Figure 5. External Clock mode clocking; tdelay_ext corresponding to the device transition delay into the awake or sleep states after an external clock transition
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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A1174
Ultrasensitive Hall Effect Latch with Internally or Externally Controlled Sample and Sleep Periods for Track Ball and Scroll Wheel Applications
the track ball can be rotated at very high speeds. If there is no output switching for the duration of the specified timeout, ttimeout, then the device switches back into the slow sampling state to conserve battery life in handheld devices. Figure 7 shows the case in which the field does not change within the ttimeout period. The behavior of the device in the presence of a rapidly changing magnetic field is shown in figure 8.
www..comduration, typical sleep time
Initially, the device operates in the slow sampling state with a tsleep_slow . The awake time duration, tawake , is common in all defined modes of operation. After the first output state transition, the device switches into the fast sampling state, with a sleep time duration, tsleep_fast , of 8 x tawake_dual. Fast input sampling ensures that the device does not miss any subsequent transitions of the incident magnetic field. This is advantageous in applications such as track ball monitoring, when
Dual Clock Mode Initial State
Set SleepTimer to tsleep_slow
Magnetic field change? NO
YES
Update device output
ReturnTimer expired ? YES Set SleepTimer to tsleep_slow
NO
Reset ReturnTimer to ttimeout
Set SleepTimer to tsleep_fast
Has SleepTimer expired? YES
NO
Sample magnetic field during tawake_dual
Figure 6. Dual Clock mode operation algorithm
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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A1174
Ultrasensitive Hall Effect Latch with Internally or Externally Controlled Sample and Sleep Periods for Track Ball and Scroll Wheel Applications
Magnetic Field (G)
50 0 -50 Off
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0
1000
2000
3000 (ms)
4000
5000
6000
Output On High Clock 0
1000
2000
3000 (ms)
4000
5000
6000
Low Supply Current (A) 300 200 100 0
0
1000
2000
3000 (ms)
4000
5000
6000
0
1000
2000
3000 (ms)
4000
5000
6000
Figure 7. Device output response in Dual Clock mode with no change of the magnetic field for the duration of ttimeout
Magnetic Field (G)
50 0 -50
0
1000
2000
Off Output
3000 (ms)
4000
5000
6000
On High Clock
0
1000
2000
3000 (ms)
4000
5000
6000
Low
0 1000 2000
Supply Current (A)
400 200 0
3000 (ms)
4000
5000
6000
0
1000
2000
3000 (ms)
4000
5000
6000
Figure 8. Device output response in Dual Clock mode with a rapid change of the magnetic field
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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A1174
Ultrasensitive Hall Effect Latch with Internally or Externally Controlled Sample and Sleep Periods for Track Ball and Scroll Wheel Applications
www..com
Application Information
It is strongly recommended that an external bypass capacitor be connected (in close proximity to the Hall sensor) between the supply and ground of the device to reduce both external noise and noise generated by the chopper stabilization technique (0.1 F is a typical value). Additionally, it is recommended that, when possible, pins be tied to either the VDD pin or ground potential in order to improve the EMC performance of the device. However, it is feasible to float the EXTERNAL_CLK and DUAL_CLK pins in the application. In the case where these pins are floating, care should be taken to locate the device as far as possible from system antennas and transceivers. The schematics on this page represent typical application circuits. (A) Device is working in Normal Clock mode. Power consumption is determined by device internal clock. (B) Device is working in Dual Clock mode. Power consumption is determined by device internal clock; frequent usage of device in fast sampling state. (C) Device is working in External Clock mode; externally-controlled power consumption. (D) Device is working in External Clock mode; high power consumption.
VDD EXTERNAL_CLK DUAL_CLK A1174 VOUT Cbypass
Vbat
(A)
GND
VDD EXTERNAL_CLK A1174 DUAL_CLK VOUT Vbat Cbypass
(B)
GND
VDD
Vbat
EXTERNAL_CLK DUAL_CLK A1174 VOUT
Cbypass
(C)
GND
VDD EXTERNAL_CLK DUAL_CLK A1174 VOUT
Vbat Cbypass
(D)
GND
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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A1174
Ultrasensitive Hall Effect Latch with Internally or Externally Controlled Sample and Sleep Periods for Track Ball and Scroll Wheel Applications
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Package EW 6-Contact MLP/DFN
1.50
F
0.74 6
F
E
0.15
0.50 6
0.30
1.00 2.00
F
0.70
1.575
A 1 1.10
1 7X D 0.08 C C
0.325 SEATING PLANE 0.38
C
PCB Layout Reference View
0.50 1 0.25 All dimensions nominal, not for tooling use (similar to JEDEC Type 1, MO-229"X2"BCD) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown 1.25 A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 SON50P200X200X80-7-M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals E Active Area Depth F Hall element (not to scale)
B
0.70
0.325
6 1.10
Copyright (c)2008, Allegro MicroSystems, Inc. The products described herein are manufactured under one or more of the following U.S. patents: 5,045,920; 5,264,783; 5,442,283; 5,389,889; 5,581,179; 5,517,112; 5,619,137; 5,621,319; 5,650,719; 5,686,894; 5,694,038; 5,729,130; 5,917,320; and other patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro's products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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